Encounter Conformal Low Power software
Product Details
- Optimizing designs for leakage and dynamic power helps designers reduce energy consumption and packaging costs. But these advanced low-power design methods also complicate the verification
task, introducing risk during synthesis and physical implementation. Full-chip, gate-level simulation is not a practical or scalable methodology for verifying todays large, complex designs.
Cadence? Encounter? Conformal? Low Power enables designers to verify and debug multimillion-gate designs optimized for low power, without simulating test vectors. It combines low-power structural
and functional checks with world-class equivalence checking to provide superior performance, capacity, and ease of use.
Features/Benefits- Minimizes silicon re-spin risk by providing complete verification coverage
- Detects low-power implementation errors early in the design cycle
- Verifies multimillion-gate designs much faster than traditional gate-level simulation
- Closes the RTL-to-layout verification gap
- Decreases risk of missing critical bugs through independent verification technology
- Country:South Korea
- telephone:82-877-4911
| Take the risk out of full-chip low-power verification |
