IC AT25D

Features
Single 2.3V - 3.6V or 2.7V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 and 3
66 MHz Maximum Operating Frequency
Clock-to-Output (tV) of 6 ns Maximum
Flexible, Optimized Erase Architecture for Code + Data Storage Applications
Uniform 4-Kbyte Block Erase
Uniform 32-Kbyte Block Erase
Uniform 64-Kbyte Block Erase
Full Chip Erase
Individual Sector Protection with Global Protect/Unprotect Feature
Four Sectors of 64 Kbytes Each
Hardware Controlled Locking of Protected Sectors via WP Pin
128-Byte Programmable OTP Security Register
Flexible Programming
Byte/Page Program (1 to 256 Bytes)
Fast Program and Erase Times
1.0 ms Typical Page Program (256 Bytes) Time
50 ms Typical 4-Kbyte Block Erase Time
250 ms Typical 32-Kbyte Block Erase Time
450 ms Typical 64-Kbyte Block Erase Time
Automatic Checking and Reporting of Erase/Program Failures
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
7 mA Active Read Current (Typical at 20 MHz)
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