Complex Multiplier 144pin CPGA Integrated Circuit

. Complex Number (16+16) * (16+16) Multiplication
. Full 32 bit- Result
. Clock Rate 20 MHz
. Twos Complement Fractional Arithmetic
. Complex Conjugation of X or Y
. 4 Cycle Fall Through
. Max. Frequency: 20 MHz

Features:

The complex multiplier adder multiplies two complex (16+16) bit words every 50 ns and can be configured to output the complete complex (32+32) bit result within a single clock cycle. The data format is fractional twos complement. The complex multiplier basically operates in two modes:

Complex Multiplier 144pin CPGA